Demand for integrated circuits (ICs) in portable electronic applications has motivated greater levels of semiconductor device integration. Many advanced semiconductor devices in development seek to leverage III-N materials that show particular promise for high voltage and high frequency applications like power management ICs and RF power amplifiers. III-N heteroepitaxial (heterostructure) field effect transistors (HFET), such as high electron mobility transistors (HEMT) and metal oxide semiconductor (MOS) HEMT, employ a semiconductor heterostructure with one or more heterojunction. GaN-based HFET devices benefit from a relatively wide bandgap (˜3.4 eV), enabling higher breakdown voltages than Si-based MOSFETs, as well as high carrier mobility. The III-N material system is also useful for photonics (e.g., LEDs), photovoltaics, and sensors, one or more of which may be useful to integrate into an electronic device platform.
It is advantageous to heteroepitaxially grow III-N films onto a silicon substrate, both from a perspective substrate cost and for the potential to more closely integrate GaN-based devices with silicon-based devices. Such GaN-on-silicon (GOS) growths are difficult however because of both lattice mismatch and mismatch of the linear thermal expansion coefficient between the nitride material and silicon substrate. During a high temperature process, such as epitaxial growth, thermal expansion mismatch can cause substrate bowing and warping. Bow is a measure of vertical displacement of the substrate surface and becomes more significant as the substrate diameter increases unless the silicon substrate thickness is increased significantly to provide the greater rigidity needed to resist larger thermal mismatch stress. Silicon substrate diameters and thicknesses are standardized however with little concern for GOS applications. As a result, a high temperature GaN growth that induces a bow of around 300 μm in a 200 mm, 725 μm thick silicon substrate may induce a bow of over 650 μm in a 300 mm, 775 μm thick silicon substrate.
Because known stress-engineered buffer layers are unable to accommodate the bow induced in silicon substrates of the diameters currently employed and under development for silicon CMOS, alternate techniques and architectures capable of reducing wafer bow would be advantageous for fabricating GaN-based devices on these large diameter silicon substrates.